1. Field of the Invention
The present invention relates to an interconnection structure of a semiconductor device, and in particular, to an interconnection structure, which is used for an interconnection layer having a line and space repeated pattern, such as a bit line and a word line of a semiconductor memory.
2. Description of the Related Art
The market of a DRAM (Dynamic Random Access Memory) used as a large capacity memory remarkably changes, and a miniaturization of the semiconductor device (or design rule) is carried out as the cost saving course to follow the above changes.
In recent years, the remarkable development has been achieved in the miniaturization of the semiconductor device; for example, the miniaturization of a capacitor, an interconnection space and an interconnection width (or gate length) has been greatly advanced.
However, a problem arises in the miniaturization of the semiconductor device. For example, the interconnection space becomes narrow, and thereby, an interconnection capacitance increases. On the other hand, the interconnection width is reduced, and thereby, an interconnection resistance increases. As a result, a problem arises such that an operating speed of memory becomes slow.
The following is a description of a device structure of the conventional semiconductor device; in this case, a DRAM is given as the example.
FIG. 1 is a top plan view showing a cell array section of the DRAM. FIG. 2 is a cross-sectional view taken along a line II—II of FIG. 1, and FIG. 3 is a cross-sectional view taken along a line III—III of FIG. 1.
In this conventional example, a memory cell array comprises array-like arranged plural trench capacitor type memory cells.
In a semiconductor substrate 100, a trench capacitor 101 is formed therein. The internal structure of the semiconductor substrate 100 and the structure of the trench capacitor 101 are not so important here; therefore, the details are omitted.
A surface region of the semiconductor substrate 100 is formed with a cell transistor. The cell transistor is composed of a source diffusion layer 103, a drain diffusion layer 104 and gate electrodes 106a and 106b. The source diffusion layer 103 is electrically connected to the trench capacitor 101. On the other hand, the drain diffusion layer 104 is connected to a bit line 110 via a contact plug 109.
A gate-insulating layer 105 is interposed between the gate electrodes 106a, 106b and the semiconductor substrate 100. The gate electrodes 106a and 106b comprises laminated first polysilicon layer 106a and second polysilicon layer 106b, respectively. Further, the gate electrodes 106a and 106b are covered with a silicon nitride layer 107.
An insulating layer 108 is formed on the cell transistor so as to fully cover the cell transistor. The surface of the insulating layer 108 is planarized. The insulating layer 108 is formed with a contact hole, which reaches the drain diffusion layer 104 of the cell transistor. The above contact plug 109 is arranged in the contact hold thus formed. Further, the contact plug 109 is made of conductive polysilicon, tungsten and the like.
A plurality of bit lines 101 extending to a column direction is formed on the insulating layer 108. The plurality of bit lines 110 is regularly laid out with a line and space pattern.
In the semiconductor device having the above device structure, the plurality of bit lines 110 has the line and space pattern; therefore, it is easy to become an object for determining the minimum size on chip layout. More specifically, a width L and a space S of the bit line 110 are set to the minimum size determined by lithography technology. Moreover, in order to make large a process margin of the bit line 110, a ratio of the width L and the space S of the bit line 110 is set to 1:1.
However, as described above, in the case where the width L and the space S (line and space) of the bit line 110 are reduced, the interconnection resistance and the interconnection capacitance increase; as a result, a problem arises such that the operating speed of memory becomes late.
Recently, an approach from a material aspect has been proposed as one course for improving the operating speed of memory. For example, the following improvement courses are taken. That is, the insulating layer arranged between interconnection lines is made of an organic-based insulating material having a low permittivity so that the interconnection capacitance can be made small. Moreover, the interconnection line is made of a low resistance material (e.g., copper) so that the interconnection resistance can be made small.
However, in the case where the above improvement course from the material aspect is taken, from the reason why the price of the material itself is expensive, a manufacturing cost of semiconductor memory increases. For this reason, eventually, it is impossible to sufficiently reduce a bit cost (manufacturing cost per bit) by the miniaturization of the semiconductor device.
Moreover, as one course for reducing the interconnection resistance, a course is taken such that a thickness of the interconnection layer is made large so as to prevent a reduction of the interconnection cross-sectional area by the reduction of the interconnection width. However, when the thickness of the interconnection layer is made large, this is a factor of increasing an area where adjacent interconnection lines face each other, and increasing the interconnection capacitance; for this reason, it is impossible to sufficiently improve the operating speed of memory.